The present invention relates to a semiconductor memory device and, more particularly, to an erasable programmable read-only memory.
An erasable programmable read-only memory (to be referred to as an EPROM hereinafter in accordance with a custom among those skilled in the art) is currently a typical non-volatile semiconductor memory device in which information stored therein can be rewritten. It is well known that a "double-gate structure" is adopted in each memory cell of EPROMs. More specifically, a floating gate electrode and a control gate electrode are insulatively provided above a semiconductor chip substrate, on which semiconductor diffusion layers serving as source and drain layers are formed spaced apart from each other.
According to the EPROMs of this type, when a positive voltage (e.g., 20 volts) is applied to a drain layer and a control gate electrode of a selected memory cell in a write mode, carriers (e.g., electrons) flow from the source to the drain. A flow of the electrons generates impact ionization near the drain layer of the selected memory cell, and some of the electrons are injected into a floating gate and trapped therein. These electrons are stored or accumulated in the floating gate. In a read mode, a read bias voltage is applied to a control gate of the selected memory cell to detect whether a current flows through a transistor structure of the memory cell, thereby performing an information read operation. Stored information can be erased either by radiating ultraviolet rays onto the chip substrate of the EPROM or by electrically releasing the carriers stored in the floating gate of the memory cell of interest.
However, according to the conventional EPROMs, an operation of partially erasing stored information is cumbersome and relatively time-consuming. For example, when ultraviolet rays are radiated to erase stored information of a desired memory cell, stored contents of all the memory cells are erased at the same time. Therefore, the same information must be rewritten in the memory cells other than the memory cell (or memory cells) to be erased. Although stored information of only a desired memory cell (or memory cells) can be electrically erased (this is known as an "electrically erasable-programmable read-only memory" or "E.sup.2 PROM"), an additional circuit for electrically erasing information is complicated in arrangement. Especially when the EPROMs are formed integrally with each other on a chip substrate of a high-speed logic LSI, the above problems become more serious in terms of a speed of accessing management of a memory unit. Assume that information of the memory unit must be rewritten during an operation of a logic circuit section. In this case, if the operation of the logic circuit section is interrupted each time the information is rewritten, a high-speed operation of the LSI cannot be expected at all.